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| P4C422 HIGH SPEED 256 x 4 STATIC CMOS RAM FEATURES High Speed (Equal Access and Cycle Times) - 10/12/15/20/25/35 ns (Commercial) - 15/20/25/35 ns (Military) CMOS for Low Power - 495 mW Max. - 10/12/15/20/25 (Commercial) - 495 mW Max. - 15/20/25/35 (Military) Single 5V10% Power Supply Separate I/O Fully TTL Compatible Inputs and Outputs Resistant to single event upset and latchup resulting from advanced process and design improvements Standard 22-pin 400 mil DIP, 24-pin 300 mil SOIC, 24-pin square LCC package and 24-pin CERPACK package DESCRIPTION The P4C422 is a 1,024-bit high-speed (10ns) Static RAM with a 256 x 4 organization. The memory requires no clocks or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL compatible. Operation is from a single 5 Volt supply. Easy memory expansion is provided by an active LOW chip select one (CS 1) and active HIGH chip select two (CS 2) as well as 3-state outputs. In addition to high performance and high density, the device features latch-up protection, single event and upset protection. The P4C422 is offered in several packages: 22-pin 400 mil DIP (plastic and ceramic), 24pin 300 mil SOIC, 24-pin square LCC and 24-pin CERPACK. Devices are offered in both commercial and military temperature ranges. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS SOIC (S4) CERPACK (F3) SIMILAR DIP (P3-1, C3-1, D3-1) LCC (L4) Document # SRAM101 REV. A 1 Revised October 2005 P4C422 MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value - 0.5 to +7 - 0.5 to VCC +0.5 - 55 to +125 Unit V Symbol TBIAS TSTG I OUT Parameter Temperature Under Bias Storage Temperature DC Output Current Value - 55 to +125 - 65 to +150 20 Unit C C mA VTERM TA V C RECOMMENDED OPERATING CONDITIONS Grade (2) Commercial Military Ambient Temp 0C to 70C -55C to 125C Gnd 0V 0V Vcc 5.0V 10% 5.0V 10% CAPACITANCES(4) (VCC = 5.0V, TA = 25C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF Output Capacitance VOUT = 0V DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VOH VOL VIH VIL VCL I IX I OZ I OS Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Clamp Diode Voltage Input Load Current Output Current (High Z) Output Short Circuit Current(3) Test Conditions IOH = -5.2 mA, VCC = Min.2.4 IOL = +8 mA, VCC = Min. P4C422 Min Max V 0.4 2.1 0.8 Unit V V V V A A mA IIN = -10 mA GND VIN VCC VOL VOUT VOH , Output Disabled VCC= Max., VOUT = GND -1.5 -10 -10 10 10 90 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current Temperature Range Commercial Military -10 90 N/A -12 90 N/A -15 90 90 -20 90 90 -25 65 90 -35 65 90 Unit mA mA Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 4. This parameter is sampled and not 100% tested. 5. Transition time is 3ns for 10, 12, and 15 ns products and 5ns for 20, 25, and 35 ns products, see Fig 1d. Timing is referenced at input and output levels of 1.5V. The output loading is equivalent to the specified IOL/IOH with a load capacitance of 15 pF (10, 12) or 30 pF (15, 20, 25, 35) as in Fig. 1a and 1b respectively. 6. Transition time is 3ns for 10, 12, and 15 ns products and 5ns for 20, 25, and 35 ns products, see Fig 1d. Transition is measured at steady state HIGH level -500mV or steady state LOW level +500mV on the output from a level on the input with load shown in Fig. 1c. 7. tW is measured at tWSA = min.; tWSA is measured at tW = min. Document # SRAM101 REV. A Page 2 of 10 P4C422 FUNCTIONAL DESCRIPTION An active LOW write enable (WE) controls the writing/ reading operation of the memory. When the chip select one (CS 1) and the write enable (WE) are LOW and the chip select two (CS 2) is HIGH, the information on data inputs (D0 through D3) is written into the addressed memory word and preconditions the output circuitry so that true data is present at the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times by eliminating the "write recovery glitch." Reading is performed with chip selct one (CS 1) LOW, chip select two (CS 2) HIGH, write enable (WE) HIGH and output enable (OE) LOW. The information stored in the addressed word is read out on the noninverting outputs (O0 through O3). The outputs of the memory go to an inactive high impedance state whenever chip select one (CS 1) is HIGH, or during the write operation when write enable (WE) is LOW. TRUTH TABLE Mode Standby Standby DOUT Disabled Read Write CS2 L X H H H CS1 X H L L L WE X X X H L OE X X H L X Output High Z High Z High Z DOUT High Z Notes: H L X HIGH Z = HIGH = Low = Don't Care = Implies outputs are disabled or off. This condition is defined as high impedance state for the P4C422. AC ELECTRICAL CHARACTERISTICS--READ CYCLE (VCC = 5V 10% except as noted, All Temperature Ranges)(2) Sym. tRC tACS tZRCS tAOS tZROS tAA Parameter Read Cycle Time (5) Chip Select Time (5) Chip Select to High-Z (6) Output Enable Time Output Enable to High-Z Address Access Time (5) (6) -10* 12 7.5 8 7.5 8 10 -12 -15 15 8 8 12 8 12 15 -20 20 12 15 12 15 20 -25 -35 35 Min Max Min Max Min Max Min Max Min Max Min Max 12 25 15 20 15 20 25 25 30 25 30 35 Unit ns ns ns ns ns ns 10 8 10 12 *VCC = 5V 5% TIMING WAVEFORM OF READ CYCLE Document # SRAM101 REV. A Page 3 of 10 P4C422 AC CHARACTERISTICS--WRITE CYCLE (VCC = 5V 10% except as noted, All Temperature Ranges)(2) Sym. tWC tZWS tWR tW tWSD tWHD tWSA tWHA tWSCS tWHCS Parameter Write Cycle Time (5) Write Enable to High-Z Write Recovery Time Write Pulse Width (5,7) (6) -10* 10 8 8 8 0 2 9 0 2 0 2 0 2 12 -12 15 10 10 11 0 2 0 4 0 2 -15 -20 20 -25 25 35 20 20 15 5 5 5 5 5 5 20 5 5 5 5 5 5 -35 Min Max Min Max Min Max Min Max Min Max Min Max 12 12 13 2 5 2 5 2 5 15 15 30 25 Unit ns ns ns ns ns ns ns ns ns ns Data Setup Time Prior to Write (5) Data Hold Time (5) Address Setup Time (5,7) 0 2 (5) Address Hold Time (5) Chip Select Setup Time 0 2 Chip Select Hold Time (5) *VCC = 5V 5% TIMING WAVEFORM OF WRITE CYCLE Document # SRAM101 REV. A Page 4 of 10 P4C422 AC TEST LOADS & WAVEFORMS Figure 1a Figure 1b Figure 1c Figure 1d Document # SRAM101 REV. A Page 5 of 10 P4C422 ORDERING INFORMATION SELECTION GUIDE The P4C422 is available in the following temperature range, speed, and package options. Temperature Range Commercial Temperature Military Temperature Package Plastic DIP SOIC Side Brazed DIP CERDIP LCC CERPACK Side Brazed DIP Military Processed* CERDIP LCC CERPACK Speed (ns) 10 -10PC -10SC N/A N/A N/A N/A N/A N/A N/A N/A 12 -12PC -12SC N/A N/A N/A N/A N/A N/A N/A N/A 15 -15PC -15SC -15CM -15DM -15LM -15FM -15CMB -15DMB -15LMB -15FMB 20 -20PC -20SC -20CM -20DM -20LM -20FM -20CMB -20DMB -20LMB -20FMB 25 -25PC -25SC -25CM -25DM -25LM -25FM -25CMB -25DMB -25LMB -25FMB 35 -35PC -35SC -35CM -35DM -35LM -35FM -35CMB -35DMB -35LMB -35FMB *Military temperature range with MIL-STD-883, Class B compliance. N/A = Not Available Document # SRAM101 REV. A Page 6 of 10 P4C422 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C3-1 22 (400 Mil) Min Max 0.200 0.014 0.026 0.035 0.060 0.008 0.015 1.100 0.360 0.410 0.400 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - SIDE BRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 D3-1 22 (400 Mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.111 0.350 0.410 0.400 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0 15 CERDIP DUAL IN-LINE PACKAGE Document # SRAM101 REV. A Page 7 of 10 P4C422 Pkg # # Pins Symbol A b c D E e k L Q S S1 F3 24 Min Max 0.060 0.090 0.015 0.022 0.004 0.009 0.630 0.330 0.380 0.050 BSC 0.008 0.015 0.250 0.370 0.026 0.045 0.085 0.005 - CERPACK CERAMIC FLAT PACKAGE Pkg # # Pins Symbol A A1 B1 D/E D1/E1 D2/E2 D3/E3 e h j L L1 L2 ND NE L4 24 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.395 0.410 0.250 BSC 0.125 BSC 0.410 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 6 6 SQUARE LEADLESS CHIP CARRIER Document # SRAM101 REV. A Page 8 of 10 P4C422 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P3-1 22 (400 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.065 0.009 0.015 1.065 1.120 0.330 0.390 0.390 0.425 0.100 BSC 0.500 0.115 0.160 0 15 PLASTIC DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A A1 b2 C D e E H h L S4 24 (300 Mil) Min Max 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.012 0.598 0.614 0.050 BSC 0.291 0.299 0.394 0.419 0.010 0.029 0.016 0.050 0 8 SMALL OUTLINE IC PLASTIC PACKAGE Document # SRAM101 REV. A Page 9 of 10 P4C422 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A ISSUE DATE 1997 Oct-05 SRAM101 P4C422 HIGH SPEED 256 x 4 Static CMOS RAM ORIG. OF CHANGE DAB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Document # SRAM101 REV. A Page 10 of 10 |
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